This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-305402, filed Oct. 4, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, more specifically, the invention relates to a semiconductor memory device capable of trimming of chip internal timing by fuse blow and redundancy replacement.
2. Description of the Related Art
In recent year, along with the ultra fine level of semiconductor manufacturing processes and the high speed of semiconductor memory devices to meet the high speed of system clocks, action margin in circuits has become small and it has been very difficult to optimize circuit actions.
Further, process fluctuations owing to complicated manufacturing processes have caused characteristics of transistor and resister to go out of the initial design targets, which in turn has made it more difficult to optimize circuit actions.
For the purpose of the optimization of circuit actions and the improvement of yield, in ordinary cases, in consideration of the influences by these process fluctuations and the like, a fuse set for trimming circuit characteristics and a fuse set for replacing redundancy of queue addresses are arranged in a chip.
With respect to fuses, a laser fuse wherein a fuse of polysilicon, metal and the like is blown by a laser beam is generally employed, while with a laser fuse, it is not possible to trim a chip after packaging, as a result, in recent years, an electric fuse wherein a fuse can be blown electrically even after packaging has come to be employed in chips.
FIG. 15 is a block diagram showing a typical constitution of such semiconductor memory device described above.
As shown in FIG. 15, a semiconductor memory device includes the number n of fuses in total, and comprises a fuse set block (Fuse Block) 1 that outputs fuse data F less than n greater than  for trimming circuit characteristics, a clock generating circuit (Control Clock Generator) 2 that can trim the generation timing of an internal clocks CLK_P/CLK_O/CLK_I to control actions of chip inside, a peripheral circuit 3 that is controlled by the internal clocks CLK_P/CLK_O/CLK_I generated from the clock generating circuit 2, an I/O circuit 4 consisting of 2 circuits, i.e., a data output buffer (Data Out Buffer) and a data input buffer (Data In Buffer), and a memory cell array 5 in which data read and write are controlled by the circuits 3 and 4 controlled by the internal clocks.
In the device shown in FIG. 15, the internal clocks CLK_P/CLK_O/CLK_I generated from the clock generating circuit 2 are internal clocks for controlling the peripheral circuit 3, the data output buffer in the I/O circuit 4, and the data input buffer respectively.
The peripheral circuit 3 works in synchronization with the internal clock CLK_P, therefore, by changing the generating timing of the clock CLK_P, the action timing in the peripheral circuit 3 may be changed optionally.
The data output buffer is a circuit for reading data from the memory cell array to the outside of the chip in synchronization with a rise edge or a fall edge, or both the edges of the internal clock CLK_O, and by changing the generating timing of the clock CLK_O, it is possible to adjust the timing of data output in optional manners.
While, the data input buffer is a circuit for take data to be written into the memory cell array into the inside of the chip in synchronization with the rise edge, or the fall edge, or both the edges of the internal clock CLK_I, and by changing the generating timing of the clock CLK_I, it is possible to adjust the timing of data input in optional manners.
In the next place, the whole actions will be explained with the case of trimming of data input timing as an example.
FIG. 16A is a diagram showing a relation between an external clock CLK and data DQ, FIG. 16B is a diagram showing a relation between an internal clock CLK_I and an input data D_IN (before trimming), and FIG. 16C is a diagram showing a relation between an internal clock CLK_I and an input data D_IN (after trimming).
As shown in FIG. 16A, the write data to the memory cell array is input from DQ PAD in synchronization with both the rise edge and the fall edge of the external clock CLK. At this moment, data is input at the timing at which the circuit action margin of the data input buffer becomes maximum to the clock. Namely, when a clock cycle is referred to as T, data is input at the timing at which a set up time Ts of certain input data to the clock and a hold time Th should become T/4.
In this way, the relation between the clock and the data is optimized at the outside of the chip, however in the actual inside of the chip, such an ideal relation is in fact not attained. This is because there is delay in the generating timing of the internal clock CLK_I owing to process fluctuations, and under the influences of LCR inside of the chip.
Now, it is assumed that the timing of the internal clock CLK_I is displaced by +xcex94t from the factors mentioned above. In this case, as shown in FIG. 16B, a setup time Tsi of data input to the chip internal data D_IN becomes T/4+xcex94t, and the circuit action margin widens, while a hold time Thi of the data input becomes T/4xe2x88x92xcex94t, and the circuit action margin become small, different from the former case.
In order to correct such imbalance of the circuit action margin, a fuse that fastens the generating timing of the internal clock CLK_I by xe2x88x92xcex94t is blown, thereby the internal clock CLK_I is trimmed, and as shown in FIG. 16C, the internal timing is coordinated with the external timing, and thereby the circuit actions are optimized.
However, since an actual chip is subject to the influence of process fluctuations, even when an identical fuse is blown, a trimming value is not always same, which is the fact at present.
Accordingly, a trimming method by the fuse blow mentioned above has held a problem that the trimming effect by fuse blow, i.e., whether the blown fuse is actually optimized to the chip concerned or not, can be known only after the fuse concerned is actually blown. As a consequence, trimming amount may be in short, or to excess in cases.
In other words, in the method for trimming by fuse blow in the prior art, it has been extremely difficult to carry out the optimized trimming to a chip, which has been a problem in the prior art.
In the method by laser fuse blow carried out before packaging, it is easily confirmed whether a fuse concerned is blown correctly or not, while when using the electric fuse after packaging a chip, there is no means for judging whether the fuse is blown correctly or not, therefore, it is not to be known until the chip is tested in actual manners, which has been another problem with the prior art.
The above is the case concerning the trimming of clock generating timing, but the conditions are same also in the cases of redundancy replacement of queue addresses.
In general, in the replacement of queue addresses by redundancy, before carrying out fuse blow, a test is carried out on a redundancy array to be determined by the queue address to be replaced, and on the basis of the result thereof, redundancy replacement is carried out.
The redundancy cell test is only for testing whether a cell is valid or not, therefore, the test is nor carried out by making a chip work at the same timing as an actual test.
Consequently, there may be cases where a test is made after redundancy replacement, action is not made correctly owing to mismatch in timing and the like.
The above inconvenience, as well as the case of the above clock generating timing, comes from the fact that by the current trimming method by fuse blow and the method of redundancy replacement, it is not possible to judge the conditions of a chip after fuse blow, until the fuse is actually blown, which has been still another problem in the prior art.
A semiconductor integrated circuit device according to an embodiment of the present invention comprises: an integrated circuit portion; a fuse element block including a programmable fuse element; and a data transfer selecting circuit that selects any one of transfer of data programmed in the fuse element to the integrated circuit portion, transfer of data input from outside to the integrated circuit portion, and transfer of data programmed in the fuse element to outside.